Voltage Generator With Adjustable Slope

ABSTRACT

A charging circuit includes a first current mirror including a first branch circuit, a second branch circuit and a third branch circuit for generating a first conduction current, a second conduction current and a third conduction current according to the input voltage, a second current mirror including a fourth branch circuit coupled to the first branch circuit and including a first channel width, and a fifth branch circuit coupled to the second branch circuit and including a second channel width, wherein a load circuit is coupled between the first current mirror and the second current mirror, and the first current mirror as well as the second current mirror correspondingly adjust values of the first conduction current, the second conduction current and the third conduction current according to the first channel width as well as the second channel width, so as to process a charging operation of the load circuit.

CROSS REFERENCE TO RELATED APPLICATIONS

This is a continuation application of U.S. application Ser. No.13/594,869 filed on Aug. 26, 2012 and entitled “Voltage Generator WithAdjustable Slope”, which is included in its entirety herein byreference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a charging circuit, and moreparticularly, to a charging circuit which can adjust a charging periodand a charging slope and provide a soft start operation.

2. Description of the Prior Art

The prior art usually utilizes a voltage generator to process a chargingoperation or a soft start operation for a MOS transistor capacitor, apolysilicon capacitor or a passive circuit. Hereinafter, the MOStransistor capacitor is realized by the metal-oxide-semiconductorfield-effect transistor (MOSEFT), which is formed from the top to thebottom as a metal layer, which can be replaced by the polycrystallinesilicon nowadays, an oxide layer and a P/N-type semiconductor layer tostructurally form a MOS-transistor-type capacitor. The oxide layer isthe silicon dioxide to be regarded as a dielectric material in thecapacitor. Width of the oxide layer and a dielectric constant of thesilicon dioxide determine a capacitance of the capacitor. Thepolycrystalline silicon is utilized to be the gate and the semiconductoris utilized to be the base, which form two terminal ends of the MOStransistor capacitor.

Please refer to FIG. 1A, FIG. 1B and FIG. 2, wherein FIG. 1A illustratesa schematic diagram of a conventional MOS transistor capacitor MOS_C fora charging operation, FIG. 1B illustrates a schematic diagram ofdifferent operational conditions of the MOS transistor capacitor MOS_Cversus different capacitances, and FIG. 2 illustrates a schematicdiagram of a terminal voltage VC1 of the MOS capacitor MOS_C atdifferent timings. As shown in FIG. 1A and FIG. 1B, the MOS transistorcapacitor MOS_C utilizes a stable current source CS for continuouslycharging operation. Due to an incremental voltage value of a gate of theMOS transistor capacitor MOS_C, the MOS transistor capacitor MOS_Cchanges capacitances thereof between a depletion capacitance C_del andan inversion capacitance C_inv, and the above capacitances correspond todifferent operational conditions. Please refer to FIG. 2, since the MOStransistor capacitor MOS_C can be either the depletion capacitance C_delor the inversion capacitance C_inv, the terminal voltage VC1 of the MOStransistor capacitor MOS_C corresponds to two lines with differentslopes at the threshold voltage Vth, which equals to 0.8 volts. Undersuch circumstances, dramatically changeable capacitances of thecapacitance of the MOS transistor capacitor MOS_C occur nearby thethreshold voltage Vth.

Also, the prior art usually utilizes solutions, such as reducingcharging currents of the MOS transistor capacitor MOS_C or increasingthe capacitance of the MOS transistor capacitor MOS_C, to slow down thecharging operation of the MOS transistor capacitor MOS_C to meetdifferent requirements. However, the mentioned two solutions still haveproblems thereof. For example, if the charging currents are reduced, aleakage current can effectively influence the charging operation of theMOS transistor capacitor MOS_C. Besides, the incremental capacitance ofthe MOS transistor capacitor MOS_C may results in extra areas needed incircuit layout to increase product cost. Therefore, it has become animportant issue to provide another charging circuit for the MOStransistor capacitor to prevent discontinuous charging voltages duringthe charging operation of the MOS transistor capacitor MOS_C, so as toadaptively provide an adjustable charging slope and an adjustablecharging period to be operated as another soft start operation.

SUMMARY OF THE INVENTION

It is therefore an objective of the invention to provide a chargingcircuit having a charging operation with an adjustable charging slope aswell as an adjustable charging period being preformed as a soft startoperation.

The present invention discloses a charging circuit comprising a firstcurrent mirror for receiving an input voltage, a second current mirrorcoupled to the first current mirror and comprising a first branchcircuit and a second branch circuit for receiving the input voltage, aswitch transistor coupled to the first current mirror and the firstbranch circuit of the second current mirror for determining a conductioncondition of the switch transistor according to a switch signal, a firstresistor comprising a first resistance, one end coupled to the switchtransistor and another end grounded, and a second resistor comprising asecond resistance, one end coupled to the second branch circuit of thesecond current mirror and another end grounded, wherein the firstcurrent mirror and the second current mirror are utilized to process acharging operation of a load circuit according to the first resistanceas well as the second resistance.

The present invention also discloses another charging circuit comprisinga first current mirror comprising a first branch circuit for generatinga first conduction current according to an input voltage, a secondbranch circuit for generating a second conduction current according tothe input voltage, and a third branch circuit for generating a thirdconduction current according to the input voltage, a second currentmirror comprising a fourth branch circuit coupled to the first branchcircuit and comprising a first channel width, and a fifth branch circuitcoupled to the second branch circuit and comprising a second channelwidth, wherein a load circuit is coupled between the first currentmirror and the second current mirror, and the first current mirror aswell as the second current mirror correspondingly adjust values of thefirst conduction current, the second conduction current and the thirdconduction current according to the first channel width as well as thesecond channel width, so as to process a charging operation of the loadcircuit.

The present invention also discloses another charging circuit comprisinga driver circuit for receiving an input voltage to generate aninitiation current, a first current mirror comprising a first branchcircuit for generating a first conduction current according to the inputvoltage and the initiation current, a second branch circuit forgenerating a second conduction current according to the input voltageand the initiation current, and a third branch circuit for generating athird conduction current according to the input voltage and theinitiation current, a second current mirror comprising a fourth branchcircuit coupled to the first branch circuit and comprising a firstchannel width, and a fifth branch circuit coupled to the second branchcircuit and comprising a second channel width, a third current mirrorcoupled to the first current mirror and comprising a sixth branchcircuit and a seventh branch circuit for receiving the input voltage, aswitch transistor coupled to the second branch circuit of the firstcurrent mirror and the sixth branch circuit of the third current mirrorfor determining a conduction condition of the switch transistoraccording to a switch signal, a first resistor comprising a firstresistance, one end coupled to the switch transistor and another endgrounded, and a second resistor comprising a second resistance, one endcoupled to the seventh branch circuit of the third current mirror andanother end grounded, wherein the first current mirror and the secondcurrent mirror are utilized to correspondingly adjust values of thefirst conduction current, the second conduction current and the thirdconduction current according to the first channel width as well as thesecond channel width, or the third current mirror is utilized to processthe charging operation of the load circuit according to the firstresistance as well as the second resistance.

These and other objectives of the present invention will no doubt becomeobvious to those of ordinary skill in the art after reading thefollowing detailed description of the preferred embodiment that isillustrated in the various figures and drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A illustrates a schematic diagram of a conventional MOS transistorcapacitor for a charging operation.

FIG. 1B illustrates a schematic diagram of different operationalconditions of the MOS transistor capacitor versus differentcapacitances.

FIG. 2 illustrates a schematic diagram of a terminal voltage of the MOScapacitor at different timings.

FIG. 3 illustrates a schematic diagram of a charging circuit accordingto an embodiment of the invention.

FIG. 4 illustrates a schematic diagram of charging operation comparisonbetween the prior art and the charging circuit according to anembodiment of the invention.

FIG. 5 illustrates a schematic diagram of another charging circuitaccording to an embodiment of the invention.

FIG. 6 illustrates a schematic diagram of another charging circuitaccording to an embodiment of the invention.

FIG. 7 illustrates a schematic diagram of another charging circuitaccording to an embodiment of the invention.

FIG. 8 illustrates a schematic comparison diagram of the chargingcircuit shown in FIG. 7 to provide different output voltages accordingto an embodiment of the invention.

FIG. 9 illustrates a schematic diagram of another charging circuitaccording to an embodiment of the invention.

FIG. 10 illustrates a schematic comparison diagram of the chargingcircuit shown in FIG. 9 to provide different output voltages accordingto an embodiment of the invention.

FIG. 11 illustrates a flow chart of a charging process according to anembodiment of the invention.

FIG. 12 illustrates a flow chart of another charging process accordingto an embodiment of the invention.

FIG. 13 illustrates a flow chart of another charging process accordingto an embodiment of the invention.

DETAILED DESCRIPTION

The embodiment of the invention can be applied to different loadingcircuits with the format/combination as a MOS transistor capacitor, apolysilicon capacitor or a passive circuit. For the simplicity, the MOStransistor capacitor is demonstrated hereinafter, and, particularly, theP-type MOS transistor capacitor is demonstrated for the explanation,which is not limiting the scope of the invention.

Please refer to FIG. 3, which illustrates a schematic diagram of acharging circuit 30 according to an embodiment of the invention. Asshown in FIG. 3, the charging circuit 30 includes a first current mirror300, a second current mirror 302, a switch transistor 304, a firstresistor 306 and a second resistor 308. The first current mirror 300includes P-type MOS transistors MP1, MP2. The second current mirror 302includes P-type MOS transistors MP3, MP4. Sources of the transistorsMP1, MP2, MP3 and MP4 receive an input voltage VIN. The switchtransistor 304 is realized as an N-type MOS transistor MN1, and a drainof the transistor MN1 is coupled to a drain of the transistor MP3. Agate of the transistor MN1 is coupled to a drain of the transistor MP2to receive a switch signal SS. A source of the transistor MN1 is coupledto the first resistor 306. Gates of the transistors MP1, MP2 are coupledto each other and to a drain of the transistor MP1, and gates of thetransistors MP3, MP4 are coupled to each other and to a drain of thetransistor MN1. A drain of the transistor MP4 is coupled to the secondresistor 308.

Similar to the prior art, the drain of the transistor MP2 is coupled toa MOS transistor capacitor MOS_C, and a conduction current I_CSgenerated by the first current mirror 300 is utilized to perform acharging operation for the MOS transistor capacitor MOS_C. In theembodiment, the switch transistor 304 receives the switch signal SS tocorrespondingly conduct the transistors MP3, MP4 of the second currentmirror 302, so as to generate conduction currents I_MP3, I_MP4. Theconduction currents I_MP3, I_MP4 pass the first resistor 306 and thesecond resistor 308 to be transformed into output voltages VOUT1, VOUT2,which can be utilized to perform the charging operation for another MOStransistor capacitor (not shown in the figure) coupled to the outputvoltages VOUT1, VOUT2.

Please refer to FIG. 4, which illustrates a schematic diagram ofcharging operation comparison between the prior art and the chargingcircuit 30 according to an embodiment of the invention. As shown in FIG.4, during the charging operation of the MOS transistor capacitor MOS_C,the physical characteristics of the MOS transistor capacitor MOS_C mayresult in generation of a turning point nearby a threshold voltage as0.8 volt of the MOS transistor capacitor MOS_C, so as to correspondinglygenerate two different charging slopes. However, the charging circuit 30of the invention utilizes the threshold voltage of 0.8 volt required forconducting the switch transistor 304 to eliminate the turning point inthe prior art. Furthermore, adjustment of a resistance ratio formed bythe first resistor 306 and the second resistor 308 can be utilized tocorrespondingly adjust slope changes of the charging slopes related tothe output voltages VOUT1, VOUT2, so as to adjust charging periodsrelated to the output voltages VOUT1 and VOUT2, respectively.

Noticeably, the embodiment shown in FIG. 4 has the first resistor 306with the resistance of 3 ohms and the second resistor 308 with theresistance of 1 ohm. Accordingly, the output voltage VOUT2 has a moregradual charging slope as a liner-charging-voltage operation than theoutput voltage VOUT1, and users are not necessary to reduce the chargingcurrents or to utilize a larger layout area of the MOS transistorcapacitor MOS_C asking for the larger capacitance for the chargingoperation. For example, to compare three lines shown in FIG. 4 forcharging voltage of 1 volt. Sequentially, the prior art is 38.83microseconds, the output voltage VOUT1 is 143.08 microseconds, and theoutput voltage VOUT2 is 196.64 microseconds. For different users'requirements, the resistances of the first resistor 306 and the secondresistor 308 can be adaptively adjusted to longer the charging period ofthe charging operation and to approximately maintain the linear chargingvoltage, so as to meet requirement for the soft start operation, whichis also in the scope of the invention.

Please refer to FIG. 5, which illustrates a schematic diagram of anothercharging circuit 50 according to an embodiment of the invention. Asshown in FIG. 5, the charging circuit 50 includes a first current mirror500 and a second current mirror 502. For the convenience, the firstcurrent mirror 500 is similar to the first current mirror 300 and thesecond current mirror 302 shown in FIG. 3, including at least a pair ofsymmetrical transistors having gates coupled to each other. Hereinafter,only partial of the symmetrical structure is depicted for explanation.The first current mirror 500 includes a first branch circuit 5000, asecond branch circuit 5002 and a third branch circuit 5004. The firstbranch circuit 5000 includes P-type MOS transistors MP5, MP6. The secondbranch circuit 5002 includes P-type MOS transistors MP7, MP8. The thirdbranch circuit 5004 includes a P-type MOS transistor MP9. The secondcurrent mirror 502 includes a fourth branch circuit 5020 and a fifthbranch circuit 5022. The fourth branch circuit 5020 includes N-type MOStransistors MN2, MN3. The fifth branch circuit 5020 includes N-type MOStransistors MN4, MN5.

Please refer to FIG. 5 again. In the first current mirror 500, thetransistors MP5 and MP6 of the first branch circuit 5000 as well as thetransistors MP7 and MP8 of the second branch circuit 5002 are realizedvia cascoded transistors, which means a drain of the transistor MP5 iscoupled to a source of the transistor MP6, a drain of the transistor MP7is coupled to a source of the transistor MP8, and sources of thetransistors MP5, MP7 and MP9 receive the input voltage VIN. In thesecond current mirror 502, the transistors MN2 and MN3 of the fourthbranch circuit 5020 as well as the transistors MN4 and MN5 of the fifthbranch circuit 5022 are realized via cascoded transistors, which means asource of the transistor MN2 is coupled to a drain of the transistorMN3, a source of the transistor MN4 is coupled to a drain of thetransistor MN5, and sources of the transistors MN3 and MN5 are coupledto a ground GND. For connection between the first current mirror 500 andthe second current mirror 502, the drain of the transistor MP6 iscoupled to the drain of the transistor MN2, and the drain of thetransistor MP8 is coupled to the drain of the transistor MN4. Besides,the drain of the transistor MP9 is coupled to the drain of thetransistor MP7. The MOS transistor capacitor MOS_C for the chargingoperation is connected between the first current mirror 500 and thesecond current mirror 502, wherein one end of the MOS transistorcapacitor MOS_C is coupled to the drain of the transistor MP8 andanother end is coupled to the drain of the transistor MP6, so as togenerate an output voltage VOUT3.

In detail, the user can pre-adjust channel widths of the fourth branchcircuit 5020 having the transistors MN2, MN3 and the fifth branchcircuit 5022 having the transistor MN4, MN5 of the second current mirror502, so as to determine a ratio of conduction currents I_5020, I_5022passing through the fourth branch circuit 5020 and the fifth branchcircuit 5022, respectively. Next, the first current mirror 500 utilizesthe transistors MP5, MP7 and MP9 to receive the input voltage VIN and togenerate conduction currents I_5000, I_5002 and I_5004. Since thetransistor MP6 is directly coupled to the transistor MN2 and thetransistor MP8 is directly coupled to the transistor MN4, acalculational result of subtracting the conduction current I_5022 from asum of the conduction currents I_5002 and I_5004 is approximatelyequivalent to the conduction current I_5004, which causes the conductioncurrent I_5004 must passes the MOS transistor capacitor MOS_C as anotherconduction path and a charging current I_ch is formed to satisfyKirchhoff's Current Law, so as to be utilized for the charging operationof the MOS transistor capacitor MOS_C. For example, the conductioncurrent passing through the fourth branch circuit 5020 is 0.5 μA, andthe conduction current passing through the fifth branch circuit 5022 is10 μA, which forms a ratio of 1:20. Under such circumstances, the firstbranch circuit 5000, the second branch circuit 5002 and the third branchcircuit 5004 are designed to have the conduction current as 0.5 μA, 10μA and 0.5 μA, respectively. Accordingly, the charging current of theMOS transistor capacitor MOS_C is 25 nA, i.e. (10.5-10)/20=25, whereinthe number 20 represents a current multiplication belonging to theconduction currents I_5020, I_5022 of the fourth branch circuit 5020 andthe fifth branch circuit 5022.

For the pairs of the cascoded transistors MP5 and MP6, MP7 and M8, MN2and MN3, and MN4 and MN5, they are utilized to stabilize the mentionedconduction currents passing through the transistors thereof, so as toprovide a larger input-stage resistance for the input voltage VIN.Certainly, those skilled in the art can modify/replace the cascodedtransistor connection to maintain the transistors MP5, MP7, MN2 and MN4only, so as to form another first branch circuit, second branch circuit,fourth branch circuit and fifth branch circuit, which is also in thescope of the invention.

Noticeably, the first current mirror 500 and the second current mirror502 are coupled to each from top to bottom and the MOS transistorcapacitor MOS_C is in parallel connected between the first currentmirror 500 and the second current mirror 502. Therefore, differentbranch circuits, which are related to the first current mirror 500 andthe second current mirror 502, coupled to each other must share the sameconduction currents. Under such circumstances, another asymmetricalbranch circuit, i.e. the transistor MP9 in the embodiment of theinvention, can be correspondingly disposed to provide extra conductioncurrent, i.e. the conduction current I_5004 in the embodiment of theinvention. Or the transistor MP7 of the second branch circuit 5002 andthe transistor MP9 of the third branch circuit 5004 can be integratedtogether to have larger conduction width, so as to directly generateanother conduction current as a sum of the conduction current I_5004 andthe conduction current I_5002 to be outputted via the second branchcircuit 5002 for processing the charging operation of the MOC transistorcapacitor MOS_C. Certainly, those skilled in the art can combine othergeneration of stable current source with symmetrical/asymmetrical branchcircuits of the current mirrors based on the same conception of theinvention as well as Kirchhoff's Current Law, so as to perform thecharging operation of the MOS transistor capacitor MOS_C. Similarly,combination of a plurality of current mirrors, a plurality of branchcircuits and the charging circuit 50 can be utilized to process thecharging operation as well, which is also in the scope of the invention.

Please refer to FIG. 6, which illustrates a schematic diagram of anothercharging circuit 60 according to an embodiment of the invention. Asshown in FIG. 6, the charging circuit 60 is similar to the chargingcircuit 50 shown in FIG. 5, and the only difference is that a sixthbranch circuit 6000 is additionally disposed to the first current mirror500 to be another first current mirror 600. In other words, the firstcurrent mirror 600 includes the first branch circuit 5000 having theP-type MOS transistors MP5, MP6, the second branch circuit 5002 havingthe P-type MOS transistors MP7, MP8, the third branch circuit 5004having the P-type MOS transistor MP9 and the sixth branch circuit 6000having P-type MOS transistors MP10, MP11. Besides, the charging circuit60 additionally disposes a bipolar junction transistor (BJT) 602 with again parameter Beta of 34.4. A collector of the BJT 602 is coupled to areference voltage source VR, a base of the BJT 602 is coupled to one endof the MOS transistor capacitor MOS_C and the drain of the transistorMP6, and an emitter of the BJT 602 is coupled to the drains of thetransistor MP11 and MN2. Under such circumstances, the transistor MP6 ofthe first branch circuit 5000 and the transistor MP11 of the sixthbranch circuit 6000 are simultaneously coupled to the transistor MN2 ofthe fourth branch circuit 5020. Connection of the other elements issimilar to the charging circuit 50 shown in FIG. 5, and is not describedhereinafter. The gain parameter Beta as 34.4 of the BJT 602 isdemonstrated as an example, and those skilled in the art can adaptivelymodify/adjust values of the gain parameter Beta to fit different users'requirements.

In detail, while the charging circuit 60 just initiates, the firstbranch circuit 5000 and the sixth branch circuit 6000 provide theconduction currents. Next, the first branch circuit 5000 and the sixthbranch circuit 6000 are turned off until the BJT 602 initiates. The BJT602 is independently operated to reduce the calculational result (i.e.the conduction current I_5004) of the charging circuit 50 via the gainparameter Beta. For current multiplication of the gain parameter Beta,the charging current of the MOS transistor capacitor MOS_C can beeffectively reduced. For example, the conduction current of the fourthbranch circuit 5020 is 3.5 μA and the conduction current of the fifthbranch circuit 5022 is 35 μA, which has a ratio of 1:10. Under suchcircumstances, the sixth branch circuit 6000, the first branch circuit5000, the second branch circuit 5002 and the third branch circuit 5004are designed to have the conduction currents as 0.1 μA, 0.1 μA, 35 μAand 0.4 μA, respectively, such that the charging current I_ch1 passingthrough the MOS transistor capacitor MOS_C is 11 nA, i.e.(35.4-35)/34.4=11. Therefore, the charging circuit 60 provides anothercharging current I_ch1 having smaller current value to process thecharging operation of the MOS transistor capacitor MOS_C, which canavoid the conventional drawback of leakage current interference orutilization of the larger layout area of the MOS transistor capacitorMOS_C, so as to provide the soft start operation of the MOS transistorcapacitor MOS_C.

Please refer to FIG. 7, which illustrates a schematic diagram of anothercharging circuit 70 according to an embodiment of the invention. Asshown in FIG. 7, the charging circuit 70 further combines the aboveembodiments including the charging circuit 30 and charging circuit 50,and only partial circuit composition/connection has to be adjusted torealize the charging operation of the MOS transistor capacitor MOS_C.The charging circuit 70 includes the second current mirror 302 of thecharging circuit 30 having two P-type MOS transistors MP3, MP4, theswitch transistor 304 having the N-type MOS transistor MN1, the firstresistor 306 and the second resistor 308. Also, the charging circuit 70includes the first branch circuit 5000 having the P-type MOS transistorsMP5, MP6, the second branch circuit 5002 having the P-type MOStransistors MP7, MP8, the third branch circuit 5004 having the P-typeMOS transistor MP9, the fourth branch circuit 5020 having the N-type MOStransistors MN2, MN3, and the fifth branch circuit 5022 having theN-type MOS transistors MN4, MN5 of the charging circuit 50. Further, thecharging circuit 70 combines the first branch circuit 5000, the secondbranch circuit 5002 and the third branch circuit 5004 as a sixth branchcircuit 7000 having P-type MOS transistors MP12, MP13 and a seventhbranch circuit 7002 having P-type MOS transistors MP14, MP15. The sixthbranch circuit 7000 as well as the seventh branch circuit 7002 areregarded as another first current mirror 700. The fourth branch circuit5020, the fifth branch circuit 5022 and an N-type MOS transistor MN6 areregarded as another second current mirror 702, and accordingly, a drivercircuit 704 is additionally disposed. The driver circuit 704 includes aswitch transistor 7040 having a P-type MOS transistor MP16, a cascodedtransistor 7042 having N-type MOS transistors MN7, MN8, and a fourthcurrent mirror 7044 having N-type MOS transistors MN9, MN10. Thetransistor MP16 includes a source for receiving the input voltage VIN, agate coupled to the gate of the transistor MP13, and a drain coupled tothe drain of the transistor MN7. The transistor MN7 includes a sourcecoupled to a drain of the transistor MN8, and a gate coupled to gates ofthe transistors MN8, MN9. The transistor MN9 includes a drain coupled toa drain of the transistor MP13, and a gate of the transistor MN10 and adrain of the transistor MN10 are coupled to the gate of the transistorMN9. Sources of the transistor MN8, MN9 and MN10 are coupled to theground GND, and a drain of the transistor MN10 is coupled to thereference voltage source VR1.

In detail, the transistor MN10 receives the reference voltage source VR1and generates the start current I_SS via copying of the transistor MN9.In the meanwhile, the transistor MP16 receives the input voltage VIN toconduct the cascoded transistor 7042 to correspondingly generate aconduction current I_7040. Thus, the transistors MP13, MP15, MP6 and MP8of the first current mirror 700 are provided with a start bias, so as todrive the first current mirror 700 and the second current mirror 702.The sixth branch circuit 7000 provides conduction currents I_7002,I_5000, I_5002 and I_5004 to the seventh branch circuit 7002, the firstbranch circuit 5000, the second branch circuit 5002 and the third branchcircuit 5004, respectively. According to the conduction current I_7002,the seventh branch circuit 7002 generates a conduction current I_7020 tobe provided to the transistors MN2, MN4 as the start bias, so as togenerate conduction currents I_5020, I_5022 of the fourth branch circuit5020 and the fifth branch circuit 5022. As to the charging operation ofthe first current mirror 700 and the second current mirror 702, detaileddescriptions can be referenced in related paragraphs of the chargingcircuit 50 and FIG. 5, which leads to a calculational result (i.e. aconduction current I_5004=25 nA) via the plurality of conductioncurrents to have another charging current I_ch2 for the chargingoperation of the MOS transistor capacitor MOS_C. Accordingly, an outputvoltage VOUT3 is generated.

Furthermore, the output voltage VOUT3 is regarded as the switch signalSS to control conduction conditions of the switch transistor 304. Thetransistors MP3, MP4 are correspondingly conducted via the conductionconditions of the switch transistor 304 to generate conduction currentsI_MP3, I_MP4. Lastly, the first resistor 306 and the second resistor 308transform the conduction currents I_MP3, I_MP4 into the output voltagesVOUT1, VOUT2. The charging operation with the adjustable charging periodas well as the charging slope are provided to process the chargingoperation of another MOS transistor capacitor (not shown in the figure)coupled to the output voltage VOUT1 or to the output voltage VOUT2. Theabove description can also be referenced in the related paragraphs ofthe charging circuit 30, FIG. 3 and FIG. 4, and is not describedhereinafter.

In simple, the charging circuit 70 can adjust the charging slope as wellas the charging period to have a more gradual charging slope as thelinear-charging-voltage operation and to satisfy the soft startoperation. Also, the asymmetrical branch circuit (i.e. the transistorMP9) can be utilized to provide the extra conduction current (i.e.conduction current I_5004) as the charging current I_ch2, so as toperform the charging operation of the MOS transistor capacitor MOS_C.Please refer to FIG. 8, which illustrates a schematic comparison diagramof the charging circuit 70 shown in FIG. 7 to provide different outputvoltages according to an embodiment of the invention. As shown in FIG.8, the output voltages VOUT1, VOUT2 and VOUT3 correspond to differentcharging lines, and the user can adaptively modify/adjust the channelwidths or the resistances related to different branch circuits tosatisfy different requirements, so as to adjust the slope changes of thecharging lines and to provide a variety of selections of the soft startoperation. For example, the embodiment of the invention utilizes thecharging current of 25 nA to process the charging operation of the MOStransistor capacitor MOS_C having an effective capacitance as 10pico-farads (pF). From beginning of the charging operation to the solidline shown in the figure, the output voltage VOUT2 is increased to 0.6volts and the charging period of the soft start operation is 529microseconds.

Please refer to FIG. 9, which illustrates a schematic diagram of anothercharging circuit 90 according to an embodiment of the invention. Asshown in FIG. 9, the charging circuit 90 combines the above embodimentsincluding the charging circuit 30 and the charging circuit 60, and has asimilar structure to the charging circuit 70. The only difference isthat the first current mirror 700 further includes the sixth branchcircuit 6000 to form another first current mirror 900.Connection/composition of other elements can be referenced to thecharging circuit 30, the charging circuit 60 and the charging circuit70, which is not described hereinafter. In comparison with the chargingcircuit 70, the charging circuit 90 further utilizes the gain parameterBeta of the BJT 602 to reduce values of the calculational result (i.e.the conduction current I_5004=12 nA) to be the charging current I_ch3.The charging current I_ch3 passing through the MOS transistor capacitorMOS_C is reduced to avoid the conventional drawback of leakage currentinterference or utilization of the larger layout area of the MOStransistor capacitor MOS_C, so as to provide the soft start operation ofthe MOS transistor capacitor MOS_C.

Please refer to FIG. 10, which illustrates a schematic comparisondiagram of the charging circuit 90 shown in FIG. 9 to provide differentoutput voltages according to an embodiment of the invention. As shown inFIG. 10, the output voltages VOUT1, VOUT2 and VOUT3 correspond todifferent charging lines, and the user can adaptively modify/adjust thechannel widths or the resistances related to different branch circuitsto satisfy different requirements, so as to adjust slope changes of thecharging lines and to provide a variety of selections of the soft startoperation. For example, the embodiment of the invention utilizes thecharging current of 12 nA to process the charging operation of the MOStransistor capacitor MOS_C having an effective capacitance as 6 pF. Frombeginning of the charging operation to the solid line shown in thefigure, the output voltage VOUT2 is increased to 0.6 volts and thecharging period of the soft start operation is 491 microseconds.

Further, the charging operation of the charging circuit 70 can besummarized as a charging process 80, as shown in FIG. 11. The chargingprocess 80 includes the steps as follows:

Step 800: Start.

Step 802: According to the reference voltage source VR1, the fourthcurrent mirror 7044 generates the start current I_SS.

Step 804: According to the start current I_SS and the input voltage VIN,the switch transistor 7040 and the cascoded transistor 7042 generate thestart bias.

Step 806: According to the start current I_SS and the start bias, thefirst current mirror 700 generates the conduction currents I_7002,I_5000, I_5002 and I_5004.

Step 808: According to the conduction current I_7002, the channel widthsof the fourth branch circuit 5020 and the fifth branch circuit 5022, thesecond current mirror 702 generates the conduction currents I_5020 andI_5022.

Step 810: According to the conduction currents I_5002, I_5004, I_5020and I_5022, the first current mirror 700 and the second current mirror702 generate the charging current I_ch2 to process the chargingoperation of the MOS transistor capacitor MOS_C.

Step 812: End.

Further, the charging operation of the charging circuit 90 can besummarized as another charging process 40, as shown in FIG. 12. Thecharging process 40 includes the steps as follows:

Step 400: Start.

Step 402: According to the reference voltage source VR1, the fourthcurrent mirror 7044 generates the start current I_SS.

Step 404: According to the start current I_SS and the input voltage VIN,the switch transistor 7040 and the cascoded transistor 7042 generate thestart bias.

Step 406: According to the start current I_SS and the start bias, thefirst current mirror 900 generates the conduction currents I_7002,I_5000, I_5002 and I_5004.

Step 408: According to the conduction current I_7002, the channel widthsof the fourth branch circuit 5020 and the fifth branch circuit 5022, thesecond current mirror 702 generates the conduction currents I_5020 andI_5022.

Step 410: According to the gain parameter Beta of the BJT 602 and theconduction currents I_5020, I_5022, the first current mirror 700 adjuststhe values of the conduction currents I_5002, I_5004.

Step 412: According to the adjusted conduction currents I_5002, I_5004and the conduction currents I_5020, I_5022, the first current mirror 700and the second current mirror 702 generate the charging current I_ch3 toprocess the charging operation of the MOS transistor capacitor MOS_C.

Step 414: End.

Further, the charging operation of the charging circuit 30 can besummarized as another charging process 20 to be added after Step 810 andStep 412, as shown in FIG. 13. The charging process 20 includes thesteps as follows:

Step 200: Start.

Step 202: According to the conduction condition of the fifth branchcircuit 5022, the switch signal SS is generated.

Step 204: The conduction condition of the switch transistor 304 iscontrolled according to the switch signal SS.

Step 206: According to the conduction condition of the switch transistor304, the second current mirror 302 generates the conduction currentsI_MP3, I_MP4.

Step 208: According to the resistances of the first resistor 306 and thesecond resistor 308, the conduction currents I_MP3, I_MP4 of the secondcurrent mirror 302 are transformed into the output voltages VOUT1, VOUT2to process the charging operation of the MOS transistor capacitor MOS_C.

Step 210: End

The detailed steps of the charging process 80, 40 and 20 can beunderstood via the related paragraphs of the charging circuit 30, 70 and90 and FIG. 3, FIG. 7 and FIG. 9, and are not described hereinafter.Thus, those skilled in the art can arbitrarily combine the chargingprocess 20 after operations of Step 810 and Step 412, or the chargingprocesses 40 and 80 can be independently operated. Certainly, thecharging process 20 can be independently operated as well, which can berealized with combination of a stable current source, like the firstcurrent mirror 300, and the switch signal to transform the conductioncurrents I_MP3, I_MP4 into the output voltages VOUT1, VOUT2, which isnot limiting the scope of the invention.

Furthermore, as shown in the table as below, the prior art utilizes thestable current source CS, as shown in FIG. 1A, to process the chargingoperation of the MOS transistor capacitor MOS_C, which leads to theproblems with weakness of minor current against noises as well as tohave larger effective capacitances. In comparison, the charging circuit70 or 90 of the invention utilizes the current difference as the minorcurrent against noises/interferences and provides a smaller effectivecapacitance corresponding to a smaller layout area. Also, the chargingperiod of the invention is approximately equivalent to the prior art tobroaden product application of the charging circuit 70 or 90.

Charging Charging Charging Charging Charging current capacitance voltageperiod process (nA) (pF) (V) (μs) Prior art 50 75 0.6 536 Charging 25 100.6 529 circuit 70 Charging 12 6 0.6 491 circuit 90

Noticeably, the embodiments of the invention are only depicted withrepresentative transistor structures. Such as the charging circuit 50shown in FIG. 5, the first current mirror 500 is realized via P-type MOStransistors, and the second current mirror 502 is correspondinglyrealized via N-type MOS transistors to output different increasingoutput voltages. Certainly, those skilled in the art can realize thefirst current mirror 500 with the N-type MOS transistors, and realizethe second current mirror 502 with the P-type MOS transistors, so as tooutput different decreasing output voltages. Certainly, replacement canbe applied to the charging circuit 30, 60, 70 or 90, and combinationhaving the P-type MOS transistors mixing the N-type MOS transistors canbe anticipated as well. Besides, the invention utilizes the P-type MOStransistor capacitor to explain related realization, and those skilledin the art can adaptively modify/change/adjust the charging circuit 30,50, 60, 70, 90 to be applied to the polysilicon capacitor, the passivecircuit or combination thereof, so as to provide the charging operationwith the adjustable charging period and the adjustable charging slopeand to provide the soft start operation as well, which is also in thescope of the invention. Additionally, the P-type MOS transistor or theN-type MOS transistor utilized in the invention has avoided occurrenceof the body effect, and it is not necessary to limit the pin positionsonto the bulk/body.

In summary, the invention provides a plurality of embodiments as acharging circuit. In the first embodiment, a switch signal controls aswitch transistor to correspondingly conduct a current mirror generatinga plurality of conduction currents. Then the plurality of conductioncurrents passing through different resistors are transformed into outputvoltages to process a charging operation of the MOS transistorcapacitor. In the second embodiment, at least two current mirrors arecoupled together, wherein one of the current mirrors has an asymmetricalbranch circuit to provide extra conduction current for the chargingoperation of the MOS transistor capacitor. In the third embodiment,combination of the first embodiment as well as the second embodiment isachieved to simultaneously perform the charging operation of the MOStransistor capacitor. IN the fourth embodiment, amendment of the secondembodiment is derived to further include another bipolar junctiontransistor, and the bipolar junction transistor provides currentmultiplication to be combined with the first embodiment for chargingoperation of the MOS transistor capacitor. Under such circumstances, theabove embodiments of the invention avoid drawbacks of interference ofleakage current generation in the prior art, or prevent utilization oflarger layout area of the MOS transistor capacitor. Also, the chargingoperation having an adjustable charging period and an adjustablecharging slope provides another soft start operation to broaden productapplication of the charging circuit, which can be applied to polysiliconcapacitors, passive circuits or combination thereof.

Those skilled in the art will readily observe that numerousmodifications and alterations of the device and method may be made whileretaining the teachings of the invention. Accordingly, the abovedisclosure should be construed as limited only by the metes and boundsof the appended claims.

What is claimed is:
 1. A charging circuit comprising: a first currentmirror comprising: a first branch circuit for generating a firstconduction current according to an input voltage; a second branchcircuit for generating a second conduction current according to theinput voltage; and a third branch circuit for generating a thirdconduction current according to the input voltage; a second currentmirror comprising: a fourth branch circuit coupled to the first branchcircuit and comprising a first channel width; and a fifth branch circuitcoupled to the second branch circuit and comprising a second channelwidth; wherein a load circuit is coupled between the first currentmirror and the second current mirror, and the first current mirror aswell as the second current mirror correspondingly adjust values of thefirst conduction current, the second conduction current and the thirdconduction current according to the first channel width as well as thesecond channel width, so as to process a charging operation of the loadcircuit.
 2. The charging circuit of claim 1, wherein the second currentmirror generates a fourth conduction current and a fifth conductioncurrent passing through the fourth branch circuit and the fifth branchcircuit, respectively, according to the first conduction current, thefirst channel width and the second channel width.
 3. The chargingcircuit of claim 2, wherein the first branch circuit and the secondbranch circuit both comprise two cascoded P-type MOS transistors, thefourth branch circuit and the fifth branch circuit both comprise twocascoded N-type MOS transistors, and a capacitive transistor comprisesone end coupled to one end of a P-type MOS transistor of the firstbranch circuit and another end coupled to one end of a P-type MOStransistor of the second branch circuit.
 4. The charging circuit ofclaim 3, wherein a calculational result is obtained from subtracting thefifth conduction current from a sum of the second conduction current andthe third conduction current such that the calculational result isutilized to process the charging operation of the load circuit.
 5. Thecharging circuit of claim 4, wherein the first current mirror furthercomprises a sixth branch circuit comprising two cascoded P-type MOStransistors.
 6. The charging circuit of claim 5, further comprising abipolar transistor comprising an emitter coupled to one end of the sixthbranch circuit, a base coupled to the load circuit as well as the oneend of the P-type MOS transistor of the first branch circuit, and acollector coupled to a reference voltage source.
 7. The charging circuitof claim 6, wherein the bipolar transistor comprises a gain parameter.8. The charging circuit of claim 7, wherein the gain parameter isutilized to process a current multiplication operation of thecalculational result, so as to process the charging operation of theload circuit.
 9. The charging circuit of claim 1, wherein the loadcircuit is a MOS transistor capacitor, a polysilicon capacitor or apassive circuit.
 10. The charging circuit of claim 1, wherein thecharging operation provides a soft start operation for the load circuit.11. The charging circuit of claim 1, wherein the second branch circuitand the third branch circuit are integrated into an integration branchcircuit providing an integration conduction current, and the integrationconduction current is a sum of the second conduction current and thethird conduction current.